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Texas Instruments
SN74AS867DWR

Logic - Counters Synch 8-Bit Up/Down Counter

Цена от 493,03 ₽ до 1 137,77 ₽

Datasheet

Наличие Texas Instruments SN74AS867DWR на складах.

Дистрибьютор

Наличие и цена

Quest

На складе 424 шт.

Обновлено 11:23 27.02.2021

1 137,77 ₽ от 1 шт.

758,51 ₽ от 2 шт.

568,88 ₽ от 5 шт.

530,96 ₽ от 42 шт.

493,03 ₽ от 111 шт.

Rochester Electronics

На складе 1922 шт.

Обновлено 10:10 28.02.2021

774,38 ₽ от 1 шт.

758,90 ₽ от 25 шт.

743,41 ₽ от 100 шт.

727,91 ₽ от 500 шт.

712,43 ₽ от 1000 шт.

Classic Components

На складе 408 шт.

Обновлено 22:47 24.02.2021

Цена по запросу.

Технические характеристики Texas Instruments SN74AS867DWR, атрибуты и параметры.

Clock Speed:

50.0 MHz

Статус жизненного цикла:

Not Listed by Manufacturer

Mounting Style:

Surface Mount

Количество бит:

Рабочая Температура:

0.00 °C to 70.0 °C

Упаковка:

Reel

Количество выводов:

RoHS:

Compliant

Logic - Counters Synch 8-Bit Up/Down Counter
Counter Logic IC
Logic Family:AS
Мин. Напряжение питания: 4,5 В
Максимальное напряжение питания: 5,5 В
Упаковка / ящик: 24-SOIC
Количество контактов: 24
Диапазон рабочих температур: от 0 ° C до + 70 ° C
Input Type:TTL
Совместимость с ведущим процессом: Да
Output Type:TTL
Соответствует RoHS: Да
These synchronous, presettable, 8-bit up/down counters feature internal-carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the count-enable (,) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the eight flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable
they may be preset to any number between 0 and 255. The load-input circuitry allows parallel loading of the cascaded counters. Because loading is synchronous, selecting the load mode disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Two count-enable (and ) inputs and a ripple-carry () output are instrumental in accomplishing this function. Both and must be low to count. The direction of the count is determined by the levels of the select (S0, S1) inputs as shown in the function table. is fed forward to enable . thus enabled produces a low-level pulse while the count is zero (all outputs low) counting down or 255 counting up (all outputs high). This low-level overflow-carry pulse can be used to enable successive cascaded stages. Transitions at and are allowed regardless of the level of CLK. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design. These counters feature a fully independent clock circuit. With the exception of the asynchronous clear on the SN74ALS867A and ´AS867, changes at S0 and S1 that modify the operating mode have no effect on the Q outputs until clocking occurs. For the ´AS867 and ´AS869, any time ENP and/or ENT is taken high, either goes or remains high. For the SN74ALS867A and SN74ALS869, any time is taken high, either goes or remains high. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The SN54AS867 and SN54AS869 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS867A, SN74ALS869, SN74AS867, and SN74AS869 are characterized for operation from 0°C to 70°C.