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Texas Instruments
SN74ACT7807-40PAG

FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 64-Pin TQFP Tray

Цена от 1 331,23 ₽ до 1 446,98 ₽

Наличие Texas Instruments SN74ACT7807-40PAG на складах.

Дистрибьютор
Наличие и цена
Rochester Electronics
На складе 1428 шт.
Обновлено 10:08 07.02.2021
1 446,98 ₽ от 1 шт.
1 418,05 ₽ от 25 шт.
1 389,11 ₽ от 100 шт.
1 360,17 ₽ от 500 шт.
1 331,23 ₽ от 1000 шт.
Corohmni
На складе 15 шт.
Обновлено 19:23 31.01.2021
Цена по запросу.
Kenton Components
На складе 50 шт.
Обновлено 21:45 01.02.2021
Цена по запросу.

Технические характеристики Texas Instruments SN74ACT7807-40PAG, атрибуты и параметры.

Тип корпуса / Кейс:
TQFP
Clock Speed:
25.0 MHz (max)
Lead-Free Status:
Lead Free
Статус жизненного цикла:
Not Listed by Manufacturer
Размер памяти:
2250 B
Mounting Style:
Surface Mount
Рабочая Температура:
70.0 °C (max)
Упаковка:
Bulk
Количество выводов:
64
RoHS:
Compliant
Supply Voltage (DC):
5.50 V (max), 5.00 V
  • FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 9 64-Pin TQFP Tray
  • IC SYNC FIFO MEM 2048X9 64-TQFP
  • The SN74ACT7807 is a 2048-word by 9-bit FIFO with high speed and fast access times. It processes data at rates up to 67 MHz and access times of 12 ns in a bit-parallel format. Data outputs are noninverting with respect to the data inputs. Expansion is easily accomplished in both word width and word depth. The write-clock (WRTCLK) and read-clock (RDCLK) inputs should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when the write-enable (WRTEN1/DP9, WRTEN2) inputs are high and the input-ready (IR) flag output is high. Data is read from memory on the rising edge of RDCLK when the read-enable (RDEN1, RDEN2) and output-enable (OE) inputs are high and the output-ready (OR) flag output is high. The first word written to memory is clocked through to the output buffer regardless of the levels on RDEN1, RDEN2, and OE. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronous to WRTCLK and RDCLK. RESET must be asserted while at least four WRTCLK and four RDCLK cycles occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7807 is characterized for operation from 0C to 70C.

Документы по Texas Instruments SN74ACT7807-40PAG, инструкции, описания, datasheet.