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Texas Instruments
SN74V283-15PZA

FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 18/64K x 9 80-Pin LQFP Tray

Цена от 4 749,10 ₽ до 5 162,05 ₽

Наличие Texas Instruments SN74V283-15PZA на складах.

Склад
Наличие и цена
Америка 1
В наличии до 1266 шт.
MOQ от 100 шт.
Цена от 4 749,10 ₽ до 5 162,05 ₽
США
На складе 1266 шт.
Обновлено 10:11 01.03.2021
5 162,05 ₽ от 1 шт.
5 058,81 ₽ от 25 шт.
4 955,57 ₽ от 100 шт.
4 852,33 ₽ от 500 шт.
4 749,10 ₽ от 1000 шт.

Технические характеристики Texas Instruments SN74V283-15PZA, атрибуты и параметры.

Тип корпуса / Кейс:
LQFP
Clock Speed:
66.7 MHz (max)
Частота:
66.7 MHz
Lead-Free Status:
Contains Lead
Статус жизненного цикла:
Active
Размер памяти:
72000 B
Mounting Style:
Surface Mount
Рабочая Температура:
70.0 °C (max)
Output Current Drive:
-250 µA
Упаковка:
Bulk
Количество выводов:
80
RoHS:
Compliant
Supply Voltage (DC):
3.15 V to 3.45 V
Voltage Nodes:
3.30 V
  • FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 18/64K x 9 80-Pin LQFP Tray
  • 32768 x 18 Synchronous FIFO Memory 80-LQFP 0 to 70
  • FIFO Logic IC
  • Frequency Max:166MHz
  • Мин. Напряжение питания: 3,15 В
  • Максимальное напряжение питания: 3,45 В
  • Package/Case:80-LQFP
  • Количество контактов: 80
  • Диапазон рабочих температур: от 0 ° C до + 70 ° C
  • Peak Reflow Compatible (260 C):No
  • Соответствует RoHS: Да
  • The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching *9/*18 data flow. There is flexible *9/*18 bus matching on both read and write ports. The period required by the retransmit operation is fixed and short. The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can beread, is fixed and short. These FIFOs are particularly appropriate for network, video, telecommunications, data communications, andother applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bitor 9-bit width, as determined by the state of external control pins' input width (IW) and output width (OW) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. An output-enable (OE) input is provided for 3-state control of the outputs. Copyright (C) 2003, Texas Instruments Incorporated Production DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Документы по Texas Instruments SN74V283-15PZA, инструкции, описания, datasheet.

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